ECE 4745

Digital ASIC Design

Course Description

Course information provided by the 2026-2027 Catalog.

This course aims to provide a strong foundation for students to understand the principle and practice of designing, implementing, testing, and evaluating standard-cell ASIC chips using automated state-of-the-art electronic design automation (EDA) tools. Topic include both basic and advanced CMOS devices, standard cells, memories, front-end flows, and back-end flows. The course includes three design projects completed in small groups. In the first design project, students build their own simple EDA toolflow including a small standard cell library, synthesis algorithm, and place-and-route algorithm to enable mapping a combinational hardware design to layout. In the second design project, students transition to using a commercial standard-cell library and commercial EDA tools for simulation, synthesis, place-and-route, static-timing analysis, power analysis, design rule checking, and layout-vs-schematic checking of a hardware accelerator of their choosing. In the third open-ended design project, students will design, implement, test, and evaluate an interesting technique in computer architecture in the context of a more complex system-on-chip.

Prerequisites ECE 4750 OR CS 4420.

Last 4 Terms Offered (None)

Learning Outcomes

• Describe concepts related to the overall ASIC design methodology, CMOS digital circuits, and EDA algorithms and explain how these concepts interact.
• Apply this understanding to new ASIC design problems within the context of balancing application requirements against technology constraints; more specifically, quantitatively assess a design's execution time in cycles, cycle time, area, and energy.
• Evaluate various design alternatives and make a compelling quantitative and/or qualitative argument for why one design is superior to the other approaches.
• Demonstrate the ability to implement and verify designs of varying complexity at the register-transfer level and to push these designs through a commercial standard-cell ASIC flow.
• Create new baseline and alternative designs at the register-transfer level, the associated effective testing strategies, and a thorough evaluation plan.
• Write comprehensive technical reports that describe designs implemented at the register-transfer level and evaluate the designs to determine the superior approach.

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